1. Field of the Invention
The present invention generally relates to multi-threaded program execution and more specifically to a two-level scheduler for multi-threaded processing.
2. Description of the Related Art
Conventional graphics processing units (CPUs) use a large number of hardware execution threads to hide both function unit pipeline latency and memory access latency. Extreme multi-threading requires a complicated thread scheduler.
Accordingly, what is needed in the art is an improved system and method for scheduling thread execution in a multi-threaded processing environment.